This invention relates to semiconductor memory devices, and more particularly to an organization for a high density dynamic metal-oxide-semiconductor (MOS) random access memory (RAM) having an array of one transistor, one capacitor memory cells.
MOS dynamic RAMs are known in the art. These memories are fabricated on a single silicon chip using known MOS technologies. Typically n-channel MOS technology is used because of its inherent performance advantages. In recent years there has been a rapid evolution of MOS dynamic RAMs toward increased density and higher performance. Each new generation of RAMs has provided a four-fold increase in storage capacity over those of the previous generation. This evolution has been made possible by advances in n-channel MOS technology and in wafer patterning techniques leading toward a shrinkage in the size of the memory cell. Today MOS RAMs having a storage capacity of 16,384 bits (i.e., 16K RAMs) are commercially available. Presently, manufacturers are starting to introduce a 65,536 bit, or 64K, RAM; see Electronics, Sept. 28, 1978, pp. 109-116.
An example of 64K RAM is described in copending application Ser. No. 10,839, filed concurrently and having a common assignee with the instant application. In the Cenker et al RAM, the memory cell array is divided into two sub-arrays each having 128 rows and 256 columns. A two sub-array organization provides the advantage of having a refresh sequence (128 cycles) which is compatible with that of older generation RAMs by allowing simultaneous refresh of a row in each sub-array. A two sub-array organization also provides improved signals for sensing by virtue of having shorter bit-lines (column conductors) and, therefore, of reduced bit-line capacitance. In addition, the Cenker et al application discloses an arrangement for reducing power dissipation when the RAM is in a read or a write mode whereby only one of the two sub-arrays is fully selected for accessing a cell, i.e., both a row and a column are selected, while the other sub-array is partially selected for performing the refresh function only, i.e., only a row is selected. Therefore, the column decoders in the partially selected sub-array remains inactive to reduce both average and peak currents.
In dynamic memories having a large number of cells such as a 64K RAM, large transient current peaks on various conductors on the chip are a major problem. One such current peak occurs when the column conductors of the array are recovered to a precharge potential (normally VDD) after a memory function is completed. The charging of the combined capacitances of all the column conductors causes a transient surge of current on the VDD power supply lines. Insofar as increasing the number of cells in a memory also increases the total capacitance of the column conductors, the magnitude of the column precharge recovery current peak also increases with the number of cells. Another large current peak occurs when all the sense amplifiers in a sub-array are latched (i.e., activated). The discharge of the capacitances coupled to the "low-going" sense amplifier nodes causes a transient surge of current primarily on the VSS power supply lines. As the number of cells in a memory is increased, the number of sense amplifiers required is increased (as many as 512 in a 64K RAM); and, therefore, the magnitude of the latching current peak also becomes greater. Large current peaks on various conductors in the memory chip interfere with proper memory operation by causing capacitive and inductive pickup of unwanted signals on other conductors and by causing voltage drops on the power supply nodes of various circuits in the memory.
In addition to interfering with proper memory operation, large current peaks also have a deleterious effect on the reliability of the memory chip. It is well known that a metallic conductor in an integrated circuit may fail through a mechanism called electromigration. The rate of such failures is proportional to the peak current densities carried by the conductor. Therefore, from the standpoint of both proper memory operation and chip reliability it is important to minimize the peak currents in a high density dynamic RAM.
In the case of a RAM having two sub-arrays of memory cells such as the above-described 64K RAM of Cenker et al the problem becomes one of reducing peak currents in the memory while keeping both sub-arrays active for at least the cell refresh function. Prior art memory organizations using two sub-arrays have shortcomings in this regard. For example, in the 16K RAM described in IEEE Journal of Solid State Circuits, October 1976, pp. 570-573, By Ahlquist et al. a two sub-array RAM is operated with one of the two sub-arrays totally inactive at a given time. Thus both average and peak currents are reduced. However, such an arrangement would not permit simultaneous refreshing of a row in each sub-array or for reading and/or writing functions to take place in one sub-array while the refresh function takes place in the other sub-array.